Text Box: NEW!! VLSI Plus now offers MIPI® CSI2 and SMIA CCP compliant compression for RAW data types. This optional feature is offered with all VLSI Plus SVR and SVT IP cores Text Box: VLSI Plus SVR-CSCP (MIPI® CSI2 + SMIA CCP Serial Video Receiver, embedded in Graphin G-Pirates product, is the testing vehicle of leading CMOS image sensor vendors, who use it extensively in production floor testing of camera modules Text Box: IP Products The world of mobile phones rapidly converts to serial interfaces between the various elements, minimizing the EMI and power consumption associated with transfer of high bandwidth video.  MIPIR (Mobile Industry Processor Interface) defines a set of specifications for serial interface between mobile processor units. MIPIR CSI2, for example, defines the interface between the image sensor and the Application Processor.  SMIA (Standard Mobile Imaging Architecture) defines, among others, the serial interface between the camera and the Application Processor (CCP2). VLSI Plus actively contributed to the creation of MIPIR CSI2 standard. The profound understanding of the standards enabled VLSI Plus engineers to introduce CSI2 compatible IP core even before the standards were finalized. This IP is now silicon proven and widely used by CMOS Image sensor vendors. The SVR-CSCP has passed UNH IOL labs interoperability tests (see News in this page). As of October 2010, it is the only CSI-Receiver IP core with IOL certificate. VLSI Plus offers a variety of IP cores, for ASIC and FPGA, compatible with MIPIR and SMIA standards. Today VLSI Plus is a contributing member to MIPIR next generation of camera serial interface specifications (CSI3), and the underlying UNIPRO and M-PHY layers. We plan to introduce CSI3 cores during 2011.

New Development

VLSI Plus  is now developing a new series of IP cores, to comply with the next generation of specifications being developed by MIPI®, including CSI3 camera serial interface, UNIPRO 1.5 and MPHY

 

VLSI Plus SVR-F (MIPI® CSI2 Receiver, FPGA version) passes MIPI extensive interoperability tests against 11 different CSI cameras.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

For a full IOL-certified interoperability report contact VLSI Plus.

 

 

 

Home Page

IP Products

ISP

VLSI Architecture

Contact Us
Text Box: .

 

  All VLSI Plus IP cores are compliant with MIPIR CSI2 standard

Products

Description

Standards

Rating

Availability

SVR-CS

 Serial Video receiver, 1-2 data lanes

 CSI2, D-PHY

 2Gbps

Now

SVR-CSCP

 Dual-Mode Serial Video receiver

 CSI2, D-PHY, CCP2

 CSI: 2Gbps
 CCP: 650Mbps

Now

SVR-CS-4

 Serial Video receiver, 1-4 data lanes

 CSI2, D-PHY

 4Gbps

Now

SVR-CSCP-4

 Dual-Mode Serial Video receiver, with 4-CSI lanes

 CSI2, D-PHY, CCP2

 CSI: 4Gbps
 CCP: 650Mbps

Now

SVR-CSCP-F

 FPGA version of SVR-CSCP, 1-4 data lanes

 CSI2, D-PHY, CCP2

 Typically 800Mbps  per lane

Now

SVT-CS

 Serial Video Transmitter, 1-2 data lanes

 CSI2

 2Gbps

Now

SVT-CSCP

 Dual Mode Serial Video Transmitter

 CSI2, CCP2

 CSI: 2Gbps
 CCP: 650Mbps

Now

SVT-CS4AP1

 Serial Video Transmitter, 1-4 data lanes

 CSI2, D-PHY

 1 Gbps per lane

 Now

SVT-CS4AP1-F

FPGA version on SVT-CS4AP1, 1-4 data lanes

CSI2, D-PHY

Typically 800Mbps  per lane

Now